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HD49323AF-01
CDS/AGC & 10-bit A/D Converter
ADE-207-262A (Z) 2nd Edition Apr. 1999 Description
The HD49323AF-01 is a CMOS IC that provides CCD-AGC analog processing (CDS/AGC) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter in a single chip.
Functions
* * * * * * * * * Correlated Double Sampling AGC Sample hold Offset compensation Serial interface control 10-bit ADC 3 V single operation (2.7 V to 3.6 V) Power dissipation: 198 mW (Typ) Maximum frequency: 20 MHz (Min)
Features
* Good suppression of CCD output low-frequency noise is achieved through the use of S/H type correlated double sampling. * A high S/N ratio is achieved through the use of a AGC type amplifier, and high sensitivity is provided by a wide cover range. * An auto offset circuit provides compensation of output DC offset voltage fluctuations due to variations in AGC amplifier gain. * AGC, standby mode, offset control, etc., is possible via a serial interface. * High precision is provided by a 10-bit-resolution A/D converter. * Version of Hitachi's previous-generation HD49322BF with improved functions and performance, including in particular an approximately 3.0 dB improvement in S/N.
HD49323AF-01
Pin Arrangement
NC BIAS VRT VRM VRB AVDD AVSS TESTC TESTY CDSIN AVDD AVSS AVSS AVDD NC NC AVDD AVSS CS SCK SDATA DVDD DVSS DVSS 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 21 40 20 41 42 19 43 18 44 17 16 45 46 15 14 47 48 13 1 2 3 4 5 6 7 8 9 10 11 12 PBLK D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 NC (Top view) 2 VRM2 CLP NC AVDD AVSS SPSIG SPBLK OBP ADCLK DVDD DVSS OE
HD49323AF-01
Pin Description
Pin No. 1 2 3 to 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol PBLK D0 D1 to D8 D9 NC OE DV SS DV DD ADCLK OBP SPBLK SPSIG AVSS AVDD NC CLP VRM2 AVSS AVDD CDSIN TESTY TESTC AVSS AVDD VRB VRM VRT Description Pre-blanking pin Digital output (LSB) Digital output Digital output (MSB) No connection pin Digital output enable control pin Digital ground (0 V) Digital power supply (3 V) Connect off-chip in common with AVDD. ADC conversion clock input pin Optical black pulse input pin Black level sampling clock input pin Signal level sampling clock input pin Analog ground (0 V) Analog power supply (3 V) Connect off-chip in common with DV DD. No connection pin Clamp voltage pin Connect a 0.22 F or more capacitor between CLP and AVSS . Reference voltage pin (for CCD offset cancel) Analog ground (0 V) Analog power supply (3 V) Connect off-chip in common with DV DD. CDS input pin Test input pin-Y Test input pin-C Analog ground (0 V) Analog power supply (3 V) Connect off-chip in common with DV DD. Reference voltage pin 3 Connect a 0.1 F ceramic capacitor between VRB and AVSS. Reference voltage pin 2 Connect a 0.1 F ceramic capacitor between VRM and AVSS . Reference voltage pin 1 Connect a 0.1 F ceramic capacitor between VRT and AVSS . I/O I O O O -- I -- -- I I I I -- -- -- -- -- -- -- I I I -- -- -- -- -- Analog(A) or Digital(D) D D D D -- D D D D D D D A A -- A A A A A A A A A A A A
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HD49323AF-01
Pin Description (cont)
Pin No. 35 36 37 38 39, 40 41 42 43 44 45 46 47, 48 Symbol BIAS NC AVSS AVDD NC AVDD AVSS CS SCK SDATA DV DD DV SS Description Internal bias pin Connect a 24 k resistor between BIAS and AV SS . No connection pin Analog ground (0 V) Analog power supply (3 V) Connect off-chip in common with DV DD. No connection pin Analog power supply (3 V) Connect off-chip in common with DV DD. Analog ground (0 V) Serial interface control input pin Serial clock input pin Serial data input pin Digital power supply (3 V) Connect off-chip in common with AVDD. Digital ground (0 V) I/O -- -- -- -- -- -- -- I I I -- -- Analog(A) or Digital(D) A -- A A -- A A D D D D D
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HD49323AF-01
Input/Output Equivalent Circuit
Pin Name Digital output D0 to D9 DIN STBY or OE Digital input ADCLK OBP SPBLK SPSIG CS SCK SDATA PBLK OE CDSIN Digital input *1 70k (Typ) Digital output Equivalent Circuit DVDD
Analog input
Connected to VRM internally CDSIN
Reference voltage input
VRT VRM VRB VRM2
+ -
VRT
VRM VRM2 VRB
+ -
Clamp
CLP
AVDD
Connected to VRM internally
CLP
Internal bias
BIAS BIAS
AVDD
Note:
1. Applies to OE and PBLK.
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HD49323AF-01
Block Diagram
ADCLK SPBLK SPSIG
VRM
18 19
16 34 33 32
TESTC 27 TESTY 27 CDSIN 27 VRM2 27
Gain select 10bit ADC Output latch circuit
VRB
VRT
11 OE
CDS
AGC
11 D9 10 D8 9 D7 8 D6 7 D5 6 D4 5 D3 4 D2 3 D1 2 D0 17 PBLK
CLP 23
Clamp circuit 17 OBP
Serial interface
Bias ganerator 35 AVSS
44 45 43 SDATA SCK CS AVDD DVDD DVSS
6
BIAS
HD49323AF-01
Internal Functions
Functional Description * CDS (Correlated Double Sampling) circuit * AGC gain selection (11-bit digital control) *1 AGC gain can be set in the range 0 dB to 34.7 dB on the (+) side, and -3.3 dB to 0 dB on the (-) side by means of 11-bit serial data. * Automatic offset adjustment is possible for the IC's offsets (CDS, AGC, ADC) by means of serial data control at power-on.*1 * Digital output enable function * Pre-blanking function Digital output can be fixed at 32 LSB * CDS offset cancel function Note: 1. Serial data control Operating Description Figure 1 shows CDS/AGC +ADC function block.
TESTC TESTY CDSIN CDS AGC
Gain select 10bit ADC Offset cancel D0 to D9
Serial interface SPBLK SPSIG CS SCK SDATA ADCLK
Figure 1 CDS/AGC +ADC Function Block 1. CDS (Correlated Double Sampling) Circuit The CCD imaging element alternately outputs a black level (A-period signal) and a signal including the black level (B-period signal). The CDS circuit extracts the differential voltage between the black level and the signal including the black level (see figure 4). Black level sampling is performed at the rising edge of the SPBLK pulse, and signal level sampling is performed at the rising edge of the SPSIG pulse. This sequence of operations extracts the differential voltage between the black level and the signal including the black level, and supplies this to the nextstage AGC circuit. 2. Feed back clamp function The clamp level is set by means of 5-bit serial data. The setting range is 32 LSB to 56 LSB, in 1 LSB steps. A serial data value of 0 gives a 32 LSB setting, and a value of 24 gives a 56 LSB setting.
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HD49323AF-01
3. AGC Circuit The AGC gain is set by means of 11-bit serial data. The setting range is -3.3 dB to 34.7 dB. Details of the data are given in the following section. The (-) side gain setting uses setting codes -81 to 0 in 0.0039-multiple steps, and the (+) side gain setting uses setting codes 0 to 1023 in 0.034 dB steps. * Detailed specifications of HD49323AF-01 AGC gain setting codes (1) To improve S/N, the AD input dynamic range has been extended to 1.4 V from the 1.0 V of the HD49322BF. (2) There are two AGC gain ranges: (+) side 0 to 34.7 dB linear gain amp. (0.034 dB/step), and (-) side 0 to -3.3 dB "multiple" linear gain amp. (0.0039 multiple/step).
Range Typ 1.4V 0V = 0 code 0.7V = 511 code 1.4V = 1023 code
Input CDS AGC
Output ADC
Considering the case where AGC gain is set so that the ADC output code is 511 when a 150 mV signal is input: The HD49322BF AGC gain setting is (code 511)/150 mV multiple = 500 mV/150 mV multiple The HD49323AF-01 AGC gain setting is (code 511)/150 mV multiple = 700 mV/150 mV multiple
Table 1 AGC Gain (+) Setting Code Table Code 0 1 2 3 510 511 512 513 1020 1021 1022 1023 BIN (D10 to D0) 000 0000 0000 000 0000 0001 000 0000 0010 000 0000 0011 dB 0.000 0.034 0.068 0.102 Table 2 AGC Gain (-) Setting Code Table Code 0 -1 -2 -3 -30 -31 -32 -33 -78 -79 -80 -81 BIN (D10 to D0) Multiple dB 0.000 000 0000 0000 1.000 111 1111 1111 0.996 -0.034 111 1111 1110 0.992 -0.068 111 1111 1101 0.988 -0.102
001 001 010 010
1111 1111 0000 0000
1110 1111 0000 0001
17.34 17.37 17.41 17.44
111 111 111 111
1110 1110 1110 1101
0010 0001 0000 1111
0.883 0.879 0.875 0.871
-1.083 -1.121 -1.160 -1.199
011 011 011 011
1111 1111 1111 1111
1100 1101 1110 1111
34.68 34.71 34.75 34.78
111 111 111 111
1011 1011 1011 1010
0010 0001 0000 1111
0.695 0.691 0.688 0.684
-3.156 -3.205 -3.255 -3.304
4. Offset cancel circuit When power is turned on, offset voltages generated by CDS, AGC, ADC, and other circuits by means of serial data control are canceled. (Refer to page 24 (Operating Sequence at Power-On).)
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HD49323AF-01
5. Digital output enable function When the OE pin is driven high, digital output goes to the high-Z state.
OE Pin High Low (or Open, GND) Digital Output High-Z state Output enable
6. Pre-blanking function When the PBLK pin is driven high, digital output is fixed at 32 LSB. However, this is valid only when the OE pin and serial data output mode settings (LINV, MINV, TEST, STBY) are low.
PBLK Pin High Low (or Open, GND) Digital Output Fixed at 32 LSB Active
7. CCD offset cancel function This function cancels the offset voltage (VOFCCD) during the optical black period of the CCD imaging element. The definition of the CCD offset voltage (VOFCCD) is given below. * The difference between the black level sampling voltage and signal level sampling voltage during the OBP period is designated V OFCCD. This value is positive when (signal level sampling voltage) > (black level sampling voltage).
Input signal for one pixel (during OBP period)
CDS input
VOFCCD (at +) VOFCCD (at -) Black level sampling point Signal level sampling point
Figure 2 Black Level Signal Level Difference during OBP Period Table 3 Serial Data Settings
When Used VOFCON bit set to 1 VOFD0--3 (4 bits) set When Not Used VOFCON bit cleared to 0
VOFCCD Cancel Function Serial data settings
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HD49323AF-01
* Determining serial set data VOFD0--3 (1) Provisional setting Serial data VOFD0--3 settings are made according to the value of VOFCCD as shown in table 4. (2) Actual setting The set data is adjusted so that the CLP pin (pin 23) voltage is closest to 1/2 AVDD when AGC gain is set to the maximum. The data obtained in (2) is used as the serial set data. Table 4
VOFCCD (mV) -110 -90 -70 -50 -30 -10 +10 +30 +50 +70 +90 +110
VOFCCD Serial Setting Data Correspondence Table (For Reference)
Serial Setting Data VOFD3 0 0 0 0 0 0 1 1 1 1 1 1 VOFD2 0 0 1 1 1 1 0 0 0 0 1 1 VOFD1 1 1 0 0 1 1 0 0 1 1 0 0 VOFD0 0 1 0 1 0 1 0 1 0 1 0 1
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HD49323AF-01
Timing Chart
Figure 3 shows the output timing.
* Sampling timing chart 0 1
2
3
4
5
6
CDSIN
N
N+1
N+2
N+3
N+4
N+5
N+6
SPBLK
SPSIG
ADCLK
D0 to D9
N-5
N-4
N-3
N-2
N-1
N
Figure 3 Output Timing * The ADC output signals (D0 to D9) are output at the rising edge of ADCLK. * The pipeline delay is 5 clocks.
* Regarding OBP
H period OBP > 12fs
Note: The phase of OBP is for a low setting of the serial data OBP INV bit.
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HD49323AF-01
Details of Timing Specifications
Details of Timing Specifications Details of the timing specifications are shown in figure 4, and the timing specifications are summarized in table 5.
* Serial data SP INV bit "Lo" setting
A period B period
CDS input SPBLK 1.4V
(1) (2) (6)-1 (5)
(3) (6)-2
(4) (8)
SPSIG ADCLK
1.4V
(7)
1.4V
* Serial data SP INV bit "Hi" setting
A period B period
CDS input SPBLK 1.4V
(1) (2) (6)-1 (5)
(3) (6)-2
(4)
SPSIG ADCLK
1.4V
(7) (8)
1.4V
Figure 4 Details of Timing Specifications
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HD49323AF-01
Table 5
No. (1) (2) (3) (4) (5) (6)-1 (6)-2 (7), (8) Note:
Each Timing Specifications
Timing Black level signal read-in time SPBLK "Lo" period Signal level read-in time SPSIG "Lo" period SPBLK rise to SPSIG rise ADCLK rise to SPBLK rise SPSIG rise to ADCLK rise ADCLK tWH Min / tWL Min Symbol t CDS1 t CDS2 t CDS3 t CDS4 t CDS5 t CDS6-1 t CDS6-2 t CDS7, 8 Min 0 11 0 11 20 25 0 22 Typ 5 1/4fADCLK 5 1/4fADCLK 1/2fADCLK -- Max 10 Typ x 1.2 10 Typ x 1.2 Typ x 1.15 -- Unit ns ns ns ns ns ns ns ns Note 1 2 1 2 2 2 2
1. Negative when data before the rising edge of SPBLK/SPSIG is sampled, and positive when data after the rising edge is sampled. 2. The polarity of SPBLK and SPSIG is for a low setting of the serial data SP INV bit. - SPBLK SPSIG 1.4V +
Detailed Timing Specifications for Digital Output Enable Control Detailed timing specifications in the case of digital output enable control are shown in figure 5. When the OE pin is high, output disable mode is entered and output goes to the high-Z state.
tLZ, tZL measurement load DVDD 2k 10pF VOL DVSS VOH DVDD/2 tHZ tZH DVSS tHZ, tZH measurement load 10pF DVSS 2k
OE
1.4V x DVDD DVDD/2
DVDD 3.0V
Digital output (D0 to D9)
tLZ
tZL
DVSS
Figure 5 Detailed Timing Specifications for Digital Output Enable Control
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HD49323AF-01
Detailed Timing Specifications for Pre-Blanking Detailed timing specifications for pre-blanking are shown in figure 6. When the PBLK pin is high, digital output is fixed at 32 LSB. However, the OE pin and serial data output mode settings (LINV, MINV, TEST, STBY) take precedence.
PBLK
1.4V x
DVDD 3.0V
VOH Digital output (D0 to D9)
tPBLK
tPBLK
VOL
Figure 6 Detailed Timing Specifications for Pre-Blanking
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HD49323AF-01
Output Code Table Table 6 Function Table
Digital Output OE STBY TEST LINV MINV PBLK D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X Hi-Z H H X X X X Hi-Z L L L L L L Table 7 as follows L H L In the table 7 below, D9 is inverted H L L In the table 7 below, D8 to D0 are inverted H H L In the table 7 below, D9 to D0 are inverted L L H LLLLHLLLLL H L L X LHLHLHLHLH L H X HHLHLHLHLH H L X LLHLHLHLHL H H X HLHLHLHLHL Note:
Operation Mode Output Hi-Z Low power standby Normal operation
Pre-blanking Test mode
1. STBY, TEST, LINV, and MINV mode setting is performed by means of serial data. 2. OE and PBLK mode setting is performed by means of external input pins. 3. Pre-blanking mode is enabled when the PBLK pin is high and all other pins are low.
Table 7
Output Code Table
D9 L L L L ... L H ... H H H H D8 L L L L ... H L ... H H H H D7 L L L L ... H L ... H H H H D6 L L L L ... H L ... H H H H D5 L L L L ... H L ... H H H H D4 L L L L ... H L ... H H H H D3 L L L L ... H L ... H H H H D2 L L L L ... H L ... H H H H D1 L L H H ... H L ... L L H H D0 Input Level L 0V H L H ... H L ... L H L H 1.4V 0.7V
Output Pin Output Step code
0 1 2 3 ... 511 512 1020 1021 1022 1023 ...
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HD49323AF-01
Absolute Maximum Ratings (Ta = 25C)
Item Power supply voltage Power dissipation Analog input voltage Digital input voltage Operating temperature Storage temperature Note: Symbol VDD(max) PD(max) VIN(max) VI(max) Topr Tstg Ratings 6.0 400 -0.3 to AVDD +0.3 -0.3 to 6.0 -10 to +85 -55 to +125 Unit V mW V V C C
1. VDD indicates AVDD and DVDD. 2. Common connection of AVDD and DVDD should be made off-chip. If AVDD and DVDD are isolated by a noise filter, the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation.
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HD49323AF-01
Electrical Characteristics (Unless othewide specified, Ta = 25C, AVDD = 3.0 V, DVDD = 3.0 V, REXT = 24 k)
Item Power supply voltage range Conversion frequency Digital input voltage Symbol VDD fCLK max fCLK min VIH Min 2.70 20 -- DVDD 2.0 x 3.0 Typ 3.00 -- -- -- Max 3.60 -- 5.5 5.0 Unit V MHz MHz V 5V amplitude input possible Digital input pins except CS, SCK, and SDATA 5V amplitude input possible CS, SCK, SDATA IOH = -2 mA IOL = +2 mA VIH = 5.0 V Digital input pins except PBLK and OE PBLK, OE Test Conditions fCLK = 20 MHz Remarks
VIL
0
--
DVDD 0.8 x 3.0
V
VIH2
DVDD 2.25 x 3.0
--
5.0
V
VIL2 Digital output voltage Digital input current VOH VOL IIH
0 DVDD -0.5 -- --
-- -- -- --
DVDD 0.6 x 3.0 -- 0.5 50
V V V A
IIH2 IIL Digital output current ADC resolution ADC integration linearity error ADC differentiation linearity error Digital output delay time Digital output hold time IOZH IOZL RES INL DNL+ DNL- tPD tHOLD
-- -50 -- -50 10 -- -- -0.8 -- 10
-- -- -- -- 10 4 0.3 -0.3 -- --
250 -- 50 -- 10 10 0.8 -- 35 --
A A A A bit LSBp-p LSB LSB ns ns
VIH = 5.0 V VIL = 0 V VOH = VDD VOL = 0 V
fCLK = 20 MHz fCLK = 20 MHz *1
CL = 10 pF
Note:
1. DNL calculate the difference of linearity error between next two codes.
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HD49323AF-01
Electrical Characteristics (Unless othewide specified, Ta = 25C, AVDD = 3.0 V, DVDD = 3.0 V, REXT = 24 k) (cont)
Item Sleep current Symbol ISLP Min -100 Typ 0 Max 100 Unit A Test Conditions Digital input pins fixed at 0 V, output pins open Digital input pins fixed at 0 V *2 RL = 2 k CL = 10 pF *3 Remarks
Standby current ADC Input range Digital output Hi-Z delay time
ISTBY VINp-p tHZ tLZ tZH tZL
-- -- -- -- -- -- -- -- 0 11 0 11 20 25 0 22 22 -60
8 (1.4) -- -- -- -- -- 66 5 1/4fADCLK 5 1/4fADCLK 1/2fADCLK -- -- -- -- --
12 -- 100 100 100 100 100 78 10 Typ x 1.2 10 Typ x 1.2 Typ x 1.15 -- -- -- -- 10
mA V ns ns ns ns ns mA ns ns ns ns ns ns ns ns ns A
Digital output PBLK delay time Quiescent current Timing specification (1) Timing specification (2) Timing specification (3) Timing specification (4) Timing specification (5) Timing specification (6-1) Timing specification (6-2) Timing specification (7) Timing specification (8) Input current
tPBLK IDD1 tCDS1 tCDS2 tCDS3 tCDS4 tCDS5 tCDS6-1 tCDS6-2 tCDS7 tCDS8 IINCDS
CL = 10 pF fCLK = 20 MHz
*3 CDSIN use *3
fCLK = 20 MHz, Black/signal level difference = 1 V, gain = 0 dB
*4
Clamp level
CLP(00) CLP(16) CLP(24)
-- -- --
(32) (48) (56)
-- -- --
LSB LSB LSB
*2
Note:
2. Items in parentheses are reference values. 3. Refer to page 12 (Details of Timing Specifications). 4. This is not transition current, but static current.
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HD49323AF-01
Electrical Characteristics (Unless othewide specified, Ta = 25C, AVDD = 3.0 V, DVDD = 3.0 V, REXT = 24 k) (cont)
Item AGC gain(-) Symbol AGC(-081) AGC(0000) AGC gain(+) AGC(0000) AGC(0128) AGC(0256) AGC(0384) AGC(0512) AGC(0640) AGC(0768) AGC(0896) AGC(1023) Min -5.3 -2.0 -2.0 2.4 6.7 11.1 15.4 19.8 24.1 28.5 32.3 Typ -3.3 0 0 4.4 8.7 13.1 17.4 21.8 26.1 30.5 34.8 Max -1.3 2.0 2.0 6.4 10.7 15.1 19.4 23.8 28.1 32.5 37.8 Unit dB dB dB dB dB dB dB dB dB dB dB Test Conditions Remarks
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HD49323AF-01
Serial Interface Specification
SDATA latched at rise of SCK *1 tINT1 SCK tsu SDATA Data fixed at rise of CS tho DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 fSCK tINT2 *2, 3
CS
Note: 1. SDATA is latched at the rise of SCK. 2. Input 16 SCK clocks while CS is low. If the number of clocks is more or less than 16, the data will be invalid. 3. If data transmission is aborted, the data is invalid.
Figure 7 Serial Interface Specification
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HD49323AF-01
Table 8 Serial Data Functions Table
Resister 0 DI 00 (LSB) DI 01 DI 02 DI 03 DI 04 DI 05 DI 06 DI 07 DI 08 DI 09 DI 10 DI 11 DI 12 DI 13 DI 14 Lo Lo AGC Gain setting (LSB) AGC Gain setting AGC Gain setting AGC Gain setting AGC Gain setting AGC Gain setting AGC Gain setting AGC Gain setting AGC Gain setting AGC Gain setting AGC Gain setting (MSB) Test mode Low setting *2 Test mode Low setting *2 Resister 1 Hi Lo SP INV SPSIG/SPBLK inversion OBP INV CIF LoNegative input HiPositive input LofCLK>10MHz HifCLK<10MHz Resister 2 Lo Hi Clamp level adjustment (LSB) Clamp level adjustment Clamp level adjustment Clamp level adjustment Clamp level adjustment (MSB) Test mode *2 Low Low Low Low High Low High High High Test mode *2 Use prohibited ALL Low Resister 3 Hi Hi
3 VOFCON LoOFF * HiON
VOFD0 (LSB) CCD offset voltage setting VOFD1 CCD offset voltage setting VOFD2 CCD offset voltage setting VOFD3 (MSB) CCD offset voltage setting Output mode setting (LINV) Output mode setting (MINV) Output mode setting (TEST) RESET LoReset mode HiNormal operation mode OFRST LoNormal operation mode HiOffset cancel mode LoNormal operation mode HiSleep mode *1
DI 15 (MSB) Output mode setting (STBY) *1 SLP
Notes: 1. STBY: Reference voltage generation circuit is in the operational state. SLP: All circuits are in the sleep state. 2. Test mode is used for IC testing, and so cannot be used. Register 2 test mode should be set in accordance with the specification at the right of the column. For other registers, the setting should only be made in the all-low state. 3. Setting of VOFCON : LoCCD offset cancel function OFF : HiCCD offset cancel function ON Timing Specifications Min Max fSCK 3MHz 50ns tINT1, 2 tsu 50ns tho 50ns
* OBP polarity OBP INV setting = Lo Negative OBP > 12fs
H period
H period OBP INV setting = Hi Positive OBP > 12fs
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HD49323AF-01
Notice for Use
1. Careful handling is necessary to prevent damage due to static electricity. 2. This product has been developed for consumer applications, and should not be used in non-consumer applications. 3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to prevent latchup, a ceramic capacitor of 0.1 F or more and an electrolytic capacitor of 10 F or more should be inserted between the ground and power supply. 4. Common connection of AVDD and DVDD should be made off-chip. If AVDD and DVDD are isolated by a noise filter, the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation. 5. If a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure below.
Analog +3.0V AVDD AVSS Noise filter DVDD DVSS Digital +3.0V DVDD DVSS Noise filter AVDD 0.01F AVSS Example of noise filter 100H 0.01F
HD49323AF-01
HD49323AF-01
6. Connect AVSS and DVSS off-chip using a common ground. If there are separate analog system and digital system set grounds, connect to the analog system. 7. When V DD is specified in the delivery specification, this indicates AVDD and DVDD . 8. No Connection (NC) pins are not connected inside the IC, but it is recommended that they be used as power supply ground pins or left open to prevent crosstalk in adjacent analog pins. 9. To ensure low thermal resistance of the package, a Cu-type lead material is used. As this material is less tolerant of bending than Fe-type lead material, careful handling is necessary. 10. The infrared reflow soldering method should be used to mount the chip. Note that general heating methods such as solder dipping cannot be used. 11. Depending on the mounting state, picture quality (crosscut noise, wave pattern, etc.) will be dependent upon the timing of the SPBLK, SPSIG, and ADCLK signals. Check the mounting state thoroughly before use. 12. Serial communication should not be performed during the effective video period, since this will result in degraded picture quality. Also, use of dedicated ports is recommended for the SCK and SDATA signals used in the HD49323AF-01. If ports are to be shared with another IC, picture quality should first be thoroughly checked. 13. At power-on, automatic adjustment of the offset voltage generated from CDS, AGC, ADC, etc., must be implemented in accordance with the power-on operating sequence (see page 24).
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HD49323AF-01
14. If the phase difference between the black level sampling voltage and the signal level sampling voltage during the CCD imaging element optical black period (the CCD offset voltage) is 30 mV or greater, the CCD offset cancel function (page 9, item 7, CCD Offset Cancel Function) must be implemented. The CCD offset voltage variation after implementation of the CCD offset cancel function should be within 20 mV. 15. The CDSIN pin is clamped at VRM ( AVDD/2) during operation. The IC may suffer permanent damage if used with a pin voltage in the range -0.3 V to AV DD + 0.3 V. Careful attention must therefore be paid to the input signals.
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HD49323AF-01
Operating Sequence at Power-On
Must be stabilized within operating power supply voltage range
VDD
0ms 0ms 0ms or or or 1V(16ms) more more more or more
4V(64ms) or more
0ms or more
RESET
(2) RESET = "Hi" (1) RESET = "Lo" (4) OFRST = "Hi" (5) OFRST = "Lo"
OFRST
HD49323AF data transfer
0ms or more
(3) Data transfer
(6) Data transfer
SPBLK TG and SPSIG Camera DSP ADCLK control start OBP etc.
Note: 1. RESET and OFRST both use serial data transmission. 2. Stable input of SPBLK, SPSIG, ADCLK, and OBP is assumed before RESET is transmitted. 3. Numbers in parentheses in the figure show the order of transfer.
Figure 8 Operating Sequence at Power-On Serial data transmission contents are shown in table 9. "X" indicates data for which the clock polarity, clamp level, etc., can be selected. See page 21 (table 8, Serial Data Functions Table) for the purpose of the data. Table 9 Serial Data
MSB 15 14 00 00 00 11 LSB 01 00 Remarks 01 01 01 10 1 V (16 ms) or more 11000XXXXXXXX01 4 V (64 ms) or more 01000XXXXXXXX01 XXXXXXXXXXXXX00 13 0 1 1 1 12 0 0 0 0 11 0 0 0 1 04 0 0 X X 03 0 0 X X 02 0 0 X X Serial Data 10 09 08 07 0000 0000 0XXX 0000 (DI) 06 05 00 00 XX XX
Order of Transfer (1) RESET = "Lo" (2) RESET = "Hi" (3) Data transfer Wait (4) OFRST = "Hi" Wait (5) OFRST = "Lo" (6) Data transfer
a) b) c) d)
e) 0 f) 0 g) 0
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HD49323AF-01
Example of Recommended External Circuit
* CDS/AGC function is used (OE control and pre-blanking function are not used) C7 1.0 C6 C5 C4 C3 C2 C1 0.1 15p 15p 15p 15p 0.1 R1 R2 R3 R4 220 220 220 220
from Timing generator
24 23 22 21 20 19 18 17 16 15 14 13 25 AVSS 26 AVDD
VRM2 CLP NC AVDD AVSS SPSIG SPBLK OBP ADCLK DVDD DVSS OE
from CCD out
+ -
C8 0.1
27 CDSIN 28 TESTY 29 TESTC 30 AVSS 31 AVDD 32 VRB 33 VRM 34 VRT 35 BIAS 36 NC R5 24k HA49323AF-01 (CDS/AGC/ADC)
C9 1/16
C12 0.1 C13 0.1 C14 0.1 C15 0.1
AVSS AVDD NC NC AVDD AVSS CS SCK SDATA DVDD DVSS DVSS
NC D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PBLK
12 11 10 9 8 7 6 5 4 3 2 1 L2 47 to Camera signal processor
37 38 39 40 41 42 43 44 45 46 47 48 C17 47/6 L1 47 C18 0.1 C19 0.1 C20 0.1 Serial data input C21 47/6
Digital 3.0V GND
Analog 3.0V
25
HD49323AF-01
Package Dimensions
Preliminary
9.0 0.2 7.0 36 25 9.0 0.2 37 24 0.5
Unit: mm
48 12
13
*0.17 0.05 0.15 0.04
1.40 1.70 Max
1 *0.21 0.05 0.19 0.04 0.75
0.08
M
1.00 0.75 0 - 8 0.50 0.10
0.10
0.13 +0.09 -0.05
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
FP-48C Conforms 0.2 g
26
HD49323AF-01
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to:
Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
27

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